`timescale 1ns/100ps
`default_nettype none


module Even_Colour_Space_Conv (	
	input logic CLOCK_50_I,
	input logic resetn,

	input logic [31:0] Y,
	input logic [31:0] U,
	input logic [31:0] V,
	input logic start,

	input logic [31:0] mulResult,
	output logic [31:0] mulOp1,
	output logic [31:0] mulOp2,


/*input logic [] mulResult1,
output logic [] mul1_op1,
output logic [] mul1_op2,
input logic [] mulResult2,
output logic [] mul2_op1,
output logic [] mul2_op2,


*/

	output logic [7:0] R,
	output logic [7:0] G,
	output logic [7:0] B,
	output logic finish
);

enum logic [3:0]{
	//S_IDLE,
	S0,
	S1,
	S2,
	S3,
	S4
}state;

logic [31:0] acc1;
logic [31:0] acc2;
logic [31:0] acc3;

always_ff @ (posedge CLOCK_50_I or negedge resetn) begin
	if (resetn == 1'b0)begin
	   acc1 <= 32'b0;
	   acc2 <= 32'b0;
	   acc3 <= 32'b0;
	   finish <= 1'b0;
	   state <= S0;
	end else begin
	   case (state)
	  /* S_IDLE: begin
	   	    acc1 <= 32'b0;
	   	    acc2 <= 32'b0;
	   	    acc3 <= 32'b0;
	   	    finish <= 1'b0;
		    state <= S0;
	   end*/
	   S0: begin
		  if (start) begin
		    acc1 <= mulResult;
		    acc2 <= mulResult;
		    acc3 <= mulResult;
		    finish <= 1'b0;
		    state <= S1;
		  end
	   end
	   S1: begin
			acc1 <= acc1 + mulResult;
			state <= S2;
	   end
	   S2: begin
		   acc2 <= acc2 - mulResult;
		   state <= S3;
	   end
	   S3: begin
		   acc2 <= acc2 - mulResult;
		   state <= S4;
	   end
	   S4: begin
		   acc3 <= acc3 + mulResult;
		   finish <= 1'b1;
		   state <= S0;
	   end
	   default: state <= S0;
	   endcase
     end
end

always_comb begin
	case(state)
	S0: begin
		mulOp1 = 32'd76284;
		mulOp2 = Y-32'd16;
	end
	S1: begin
		mulOp1 = 32'd104595;
		mulOp2 = V-32'd128;
	end
	S2: begin
		mulOp1 = 32'd25624;
		mulOp2 = U-32'd128;
	end
	S3: begin
		mulOp1 = 32'd53281;
		mulOp2 = V-32'd128;
	end
	S4: begin
		mulOp1 = 32'd132251;
		mulOp2 = U-32'd128;
	end
	endcase
end
assign R = acc1[23:16];
assign G = acc2[23:16];
assign B = acc3[23:16];

endmodule
        